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APRIL 2004
PRODUCT BRIEF
FEATURES
XRT94L31
REV. P1.0.0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
GENERAL DESCRIPTION
The XRT94L31 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/demapping functions from either the STS-3 or STM-1 data stream. The XRT94L31 interfaces directly to the optical transceiver. The XRT94L31 processes the section, line and path overhead in the SONET/SDH data stream. The processing of path overhead bytes within the STS-1s or TUG-3s includes 64 bytes for storing the J1 bytes. Path overhead bytes can be accessed through the microprocessor interface or via serial interface. The XRT94L31 uses the internal E3/DS3 DeSynchronizer circuit with an internal pointer leak algorithm for clock smoothing as well as to remove the jitter due to mapping and pointer movements. These De-Synchronizer circuits do not need any external clock reference for its operation. The SONET/SDH transmit blocks allow flexible insertion of TOH and POH bytes through both Hardware and Software. Individual POH bytes for the transmitted SONET/SDH signal are mapped either from the XRT94L31 memory map or from external interface. A1, A2 framing pattern, C1 byte and H1, H2 pointer byte are generated. The SONET/SDH receive blocks receive SONET STS-3 signal or SDH STM-1 signal and perform the necessary transport and path overhead processing. The XRT94L31 provides a line side APS (Automatic Protection Switching) interface by offering redundant receive serial interface to be switched at the frame boundary. The XRT94L31 provides 3 mappers for performing STS-1/VC-3 to STS-1/DS3/E3 mapping function, one for each STS-1/DS3/E3 framers. A PRBS test pattern generation and detection is implemented to measure the bit-error performance. A general-purpose microprocessor interface is included for control, configuration and monitoring.
* Provides DS3/ E3 mapping/de-mapping for up to 3
tributaries through SONET STS-1 or SDH AU-3 and/or TUG-3/AU-4 containers
* Generates and terminates SONET/SDH section,
line and path layers
* Integrated SERDES with Clock Recovery Circuit * Provides SONET frame scrambling and
descrambling
* Integrated Clock Synthesizer that generates 155
MHz and 77.76 MHz clock from an external 12.96/ 19.44/77.76 MHz reference clock
* Integrated 3 E3/DS3/STS-1 De-Synchronizer circuit
that de-jitter gapped clock to meet 0.05UIpp jitter requirements
* Access to Line or Section DCC * Level 2 Performance Monitoring for E3 and DS3 * Supports mixing of STS-1E and DS3 or E3 and
DS3 tributaries
* E3 and DS3 framers for both Transmit and Receive
directions
* Complete Transport/Section Overhead Processing
and generation per Telcordia and ITU standards
* Full line APS support for redundancy applications * Loopback support for both SONET/SDH as well as
E3/DS3/STS-1
* Boundary scan capability with JTAG IEEE 1149 * 8-bit microprocessor interface * 3.3 V 5% Power Supply; 5 V input signal
tolerance
* -40C to +85C Operating Temperature Range * Available in a 504 Ball TBGA package
APPLICATIONS
* Network switches * Add/Drop Multiplexer * W-DCS Digital Cross Connect Systems
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT94L31
REV. P1.0.0
PRODUCT BRIEF
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
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BLOCK DIAGRAM OF THE XRT94L31
Rx ST S Rx ST S TO H TOH P r o cess o r Pr o ces s o r Blo c k Blo c k
T x O ve rhe a d T x Ov e rhe a d Da t a In p ut Da ta In p ut In te rf ac e In te rf Bloc kac e Bloc k T x HDL C T x HDL C C o ntro lle r C o ntro lle r
Rx ST S Rx ST S PO H PO H P r o cess o r Pr o ces s o r Blo c k Blo c k
T x SO NE T T x SO NE T POH POH Pr o ces s o r Pr o ces s o r Bloc k Bloc k
Tx STS Tx S TS TO H TO H Pr o ces s o r P r o cess o r Bloc k Bloc k Prim a ry & Prim a ry & Re du nd a n t Re du nd a n t T x S TS T x STS PEC L P EC L In te rf ace In te rf Blo c k ac e Blo c k
Tx S TS Tx STS Te le c o m Te le c o m Bus Bu s Blo c k Blo ck
T x Pa y loa d T x Pa y lo a d Dat a In p ut Da ta In p ut In terf ac e In te rf ac e
T x DS3 /E3 T x DS3 /E3 Fra m e r Fram er Bloc k Bloc k
T x DS3 /E3 T x DS3 /E3 M a pp e r M app e r Bloc k Bloc k Rx D S 3/ E3 Rx D S 3 / E3 M a pp e r M a pp e r J it te r At te nu a to r J it te r At te nu a to r Bloc k Bloc k Rx SO NET Rx SO NET PO H PO H Pr o ces s o r Pr o ces s o r Bloc k Bloc k
Rx Pa y lo ad Rx O u t pu Da ta Pa y lo atd Da ta O u t pu t In terf ac e In te rf ac e
Rx H DL C Rx H DL C C o ntro lle r C o ntro lle r
Rx D S 3/ E3 Rx D S 3 / E3 Fra m e r Fram er Bloc k Bloc k
T x S TS T x STS TO H TO H P r o cess o r Pr o ces s o r Blo c k Blo c k
Rx O ve rhe a d Rx O v e rhe a d Da ta O u t pu t Da ta O u t pu t In terf ac e In te k Blocrf ac e Bloc k
T x S TS T x STS PO H PO H P r o cess o r Pr o ces s o r Blo c k Blo c k
Prim a ry & Prim a ry & Re du nd a n t Re du nd a n t Rx ST S Rx ST S TO H TO H Pr o ces s o r Pr o ces s o r Blo c k Blo c k Prim a ry & RePrim aa n t& du nd ry Re du nd a n t C DR C DR Blo c k Blo c k
Rx ST S Rx ST S Te le c o m Te le c o m Bu s Bu s Blo ck Blo c k Prim a ry & Prim ary & Re du nd a n t Re du nd an t Rx ST S Rx ST S PEC L PEC L In te rf ac e In te rf Blo c k ac e Blo ck
Ch a nn e l 0 Ch a nn e l 1 Ch a nn e l 2
ORDERING INFORMATION
PART NUMBER XRT94L31IB PACKAGE TYPE 35 x 35mm 504 Lead TBGA OPERATING TEMPERATURE RANGE -40C to +85C
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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
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PRODUCT BRIEF
PACKAGE OUTLINE DRAWING
504 TAPE BALL GRID ARRAY (35 MM X 35 MM - TBGA) BOTTOM VIEW
XRT94L31
REV. P1.0.0
(A 1 corner feature is m fgr option)
Note: The control dimension is in millimeter.
INCHES MIN MAX 0.051 0.067 0.020 0.028 0.031 0.039 1.370 1.386 1.300 BSC 0.024 0.035 0.050 BSC 0.006 0.012 MILLIMETERS MIN MAX 1.30 1.70 0.50 0.70 0.80 1.00 34.80 35.20 33.02 BSC 0.60 0.90 1.27 BSC 0.15 0.30
SYMBOL A A1 A2 D D1 b e P
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XRT94L31
REV. P1.0.0
PRODUCT BRIEF
NOTES
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
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NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2004 EXAR Corporation Datasheet April 2004. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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